Meta SoC Processors
The Meta family of 32-bit SoC processor IP cores is a unique range of embedded processors that use hardware multi-threading to combine both general purpose and DSP capabilities with exceptional tolerance to SoC system latencies while also delivering new levels of real-time response, that makes them ideal for SoC applications. By using Imagination’s underlying architecture that is built from the ground up to support hardware multi-threading, Meta processors are ideally suited to high performance, real time applications where high data rates and sophisticated real time event handling are critical. Meta cores are used in many of Imagination’s own IP cores and SoC platform IP solutions.
Hardware multi-threading is a key technology for Imagination – most of our IP cores use this approach to extract the maximum possible processor performance from every clock cycle. Many conventional processors are regularly stalled while waiting for memory requests to complete, causing as much as 50% of the processing resource to be wasted. Meta’s unique implementation of multi-threading enables it to change between hardware contexts each clock cycle, with up to four threads supported. This means for example that while a memory request for a Linux application on one thread is being resolved, an audio decoder can be progressed on another thread, data progressed though a communications protocol stack on another, and real-time hardware events serviced on another thread. Each thread sees the processor as its own, creating in effect up to four virtual processors utilising a single datapath and coherent cache. This unique approach to embedded processor design enables Meta to deliver up to twice the measurable throughput (e.g., Dhrystone) for the same clock speed and silicon area to comparable, state-of-the-art conventional processors.
Each thread in a Meta can be configured to be either to be 'GP (general purpose)' or 'DSP'. The GP threads utilise a highly optimized RISC-like instruction set, with smaller footprint instruction sets also available to minimize code size. Each DSP thread adds ALU resources and more registers to enable the processor to execute advanced DSP algorithms such as audio codecs, modems and more.
Meta processors run a wide range of operating systems, including full Linux (both single processor and SMP), and our own MeOS RTOS (Real Time Operating System). Indeed, Meta is the only processor architecture able to support multiple OSs without the need for any virtualisation layer – the underlying architecture inherently delivers this capability. Threads running low-level tasks can also be run natively without any OS for maximum efficiency. SMP Linux enables the benefits of multi-processing and hardware multi-threading to be brought together under a familiar Linux environment, enabling software engineers to take advantage of many of the benefits of hardware multi-threading without having to write any special code.
The Meta architecture also includes advanced scheduling features such as AMA (Automatic MIPS Allocation) that enables the system designer to adjust what percentage of total MIPS is made available to each thread. Since AMA is implemented in hardware, final system performance can be adjusted to minimize software rebuilds.
The Meta Series2 IP core family comprises three IP cores, all sharing a common instruction set and architecture. This allows customers to start with a low or mid-range Meta, then upgrade to higher levels of capability as experience with multi-threading grows and SoC architects see the benefits of using Meta processors across multiple blocks in a SoC.
Meta HTP Applications Processors
The Meta HTP family delivers the ultimate combination of powerful general purpose 32-bit processor with high performance DSP and low level control – all in a single, unified datapath and cache. Capable of running all OSs – and different OSs on each thread if desired – the Meta HTP is the perfect solution for embedded SoC processor resources. Most configurations of HTP contain either two or four threads, with at least one configured for DSP and at least one thread used for full Linux. Meta HTP cores are capable of up to 400MHz operation on a 65LP process, and up to 700MHz operation on a 65G process.
Meta MTP Embedded Processors
The Meta MTP family is designed to deliver the benefits of multi-threading and high performance DSP. Typically configured with two threads, Meta MTP processors have reduced ALU and cache resources to minimize die size, and usually use an RTOS or native execution for applications. They are ideal for multimedia processing such as audio or communications. Meta MTP cores are used in several of Imagination’s platform IP solutions and IP cores, where a mix of low-level control and DSP or other mathematically intense processing tasks are required. Applications developed for a Meta MTP can usually be moved to larger Meta HTP processors without modification, offering an excellent upgrade path as applications mature and expand.
Meta LTP Embedded Microcontrollers
The Meta LTP, and its predecessor MTX, are deeply embedded, single threaded workhorses for SoCs. Its simplified cache-less memory architecture and excellent external event interfacing capabilities delivers up to 400MHz operation in a standard 65LP process. It's the ideal choice for low-level control and data flow processing, and is also used extensively in Imagination’s own IP cores.